The present invention generally relates to semiconductor devices and more particularly to a semiconductor device having an ohmic contact and a Schottky contact respectively containing Au and Al as primary component, such as a HEMT or MESFET, and a fabrication process thereof. It should be noted, however, that the present invention is by no means limited to a HEMT or MESFET, but is applicable also to other semiconductor devices including Si semiconductor devices.
Compound semiconductor devices use a compound semiconductor material for the active part of the semiconductor device such as a channel layer and achieves a very high operational speed due to the characteristically small effective mass of electron in such a compound semiconductor material. Thus, HEMTs and MESFETs are used extensively in microwave applications such as portable telephones or satellite receivers.
In a HEMT or MESFET, a Schottky gate electrode is provided for controlling the flow of electrons through a channel layer from an ohmic source electrode to an ohmic drain electrode, wherein a refractory metal such as W has been used for the Schottky gate electrode due to the small resistance of W. On the other hand, in view of reducing the resistance of the Schottky gate electrode further, it has become apparent that a gate electrode having an inverted T-shape structure is advantageous, and in relation to this, the use of Al, which is a material used traditionally for the gate electrode of old generation compound semiconductor devices, is regaining interest for the gate electrode of modern, leading edge compound semiconductor devices.
When using Al for the gate electrode of a compound semiconductor material, on the other hand, it is necessary to provide a barrier layer for suppressing diffusion of Al from the gate electrode to a wiring pattern formed of Au or an Au alloy, the wiring pattern being provided for interconnecting the active devices such as HEMT in an integrated circuit.
FIGS. 1A-1C show the process of fabricating a conventional HEMT 10.
Referring FIG. 1A, an undoped buffer layer (not shown) of GaAs is provided on a semi-insulating GaAs substrate 11 by an MOVPE process or MBE process, and an active layer 12 of undoped GaAs is provided further on the buffer layer by a similar epitaxial process. Further, an electron supplying layer 13 of n-type AlGaAs is grown epitaxially on the active layer 12, and there is formed a two-dimensional electron gas 12A in the active layer 12 along an interface to the electron supplying layer 13.
The electron supplying layer 13 is covered by a cap layer 14 of n.sup.+ -type GaAs, wherein the cap layer 14 is formed with a recess 14A exposing the electron supplying layer 13, and a Schottky electrode of Al is provided on the exposed part of the electron supplying layer 13 as a gate electrode. Further, an ohmic electrode 16 of AuGe/Au or AuGe/Ni/Au structure is provided on the cap layer 14 as a source electrode or a drain electrode. Further, a device isolation region 17 is provided at the outer side of the ohmic electrode 16 by an ion implantation of a deep impurity element such as Fe or O, such that the device isolation region 17 penetrate through the active layer 12 and reaches the substrate 11.
In the actual process, a resist layer is formed after the cap layer 17 is formed but before the formation of the gate recess 14A, followed by a photolithographic patterning process thereof so as to expose the surface of the cap layer 17 on which the ohmic electrode 16 is to be formed. Further, a conductive layer of the AuGe/Au or AuGe/Ni/Au structure is deposited on the resist pattern thus formed such that the ohmic electrode 16 is formed on the exposed surface of the cap layer 17. By lifting off the resist pattern, the ohmic electrode 16 is left on the cap layer 14 as indicated in FIG. 1A.
The formation of the gate electrode 15 proceeds as follows.
After the formation of the ohmic electrode 16 and removal of the resist pattern, a new resist layer is deposited on the cap layer 17 so as to cover the ohmic electrode 16, followed by a photolithographic patterning process to expose a part of the cap layer 17 on which the gate recess 14A is to be formed. Next, a dry etching process is applied to the exposed part of the cap layer 14 while using the resist pattern thus formed as a mask, so as to form the gate recess 14A, and an Al layer is deposited on the resist pattern thus formed uniformly, such that the Al layer fills the gate recess 14A. By lifting off the resist pattern, the gate electrode 15 of Al is left in the gate recess 14A in Schottky contact with the underlying electron supplying layer 13.
Next, in the step of FIG. 1B, a resist layer 18 is deposited on the structure of FIG. 1A, followed by a patterning process to expose the ohmic electrode 16 and the Schottky electrode 15. The resist pattern 18 thus formed is then subjected to reflowing, and a diffusion barrier layer 20 of TiWN is deposited thereon, with an intervening Ti layer 19 between the resist pattern 18 and the diffusion barrier layer 20. Further, a gold (Au) layer 21 is deposited on the TiN layer 20.
Further, in the step of FIG. 1C, the Au layer 21 and the underlying TiWN/Ti layers 19 and 20 are patterned by a photolithographic process to form interconnection patterns 21A and 21B. Further, the underlying resist pattern 18 is also removed.
In the structure of FIG. 1C, the diffusion barrier layer 20 prevents the formation of high resistance layer in the Au layer 21 caused by reaction with Al, by suppressing the diffusion of Al from the gate electrode 15 to the Au layer 21. Further, the Ti layer 19 underneath the diffusion barrier layer 20 prevents the nitridation of the Al gate electrode 15, which in turn is caused by N released from the nitride diffusion barrier layer 20. In the construction of FIG. 1C, it should be noted that a TiN layer may be used for the diffusion barrier layer 20 in place of the TiWN layer. The Ti layer 19 also acts as an adhesion layer between the ohmic electrode 16 and the TiN layer 20 or between the gate electrode 15 and the TiN layer 20.
In the foregoing patterning step of FIG. 1C, there is a problem in that a part of the Ti layer 19 remains unetched due to the oxide formation which tends to occur on the surface of the Ti layer 19 when the Ti layer 19 is patterned by an RIE process using SF.sub.6 as an etching gas. Further, there may be a redeposition of Ti which is once removed by the etching process. It should be noted that such a residue of Ti is formed uniformly all over the device except for the part covered by the interconnection pattern 21A or 21B and tends to cause a short-circuit or other undesirable problems. Thus, the device including such a Ti residue has been rejected as a defective device, while such a rejection reduces the yield of the semiconductor device substantially.
It is known that the foregoing problem of Ti residue can be reduced by reducing the thickness of the Ti layer 19. However, the inventor of the present invention has discovered that such a reduction in the thickness of the Ti layer 19 increases the contact resistance, particularly in the case of the Ti layer 19 covering the Al gate electrode 15.
FIG. 2 shows the relationship between the contact resistance and the thickness of the Ti layer 19 covering the Al gate electrode 15, wherein the vertical axis represents the resistance for an area having a size of 5 .mu.m.times.5 .mu.m.
Referring to FIG. 2, it can be seen that the contact resistance increases sharply when the thickness of the Ti layer 19 is reduced below about 100 .ANG..
The result of FIG. 2 suggests an interpretation that the reduction of thickness of the Ti layer 19 diminishes the effect of gettering of oxygen remaining on the Al gate electrode 15 and that N atoms contained in the TiWN layer 20 on the Ti layer 19 may cause a transit through the thin Ti layer 19 and reach the underlying Al gate electrode 15. It should be noted that such a diffusion of N induces a formation of high resistance AlN in the gate electrode 15.
The problem of the Ti residue formation may be avoided by forming a Ti layer selectively on the gate electrode 15 while omitting the same from the surface of the ohmic electrode 16. In this case, however, the bonding strength of the TiWN layer 20 contacting directly with the ohmic electrode 16 is reduced substantially and the TiWN layer 20 may be peeled off from the ohmic electrode 16. As noted before, the Ti layer 19 acts also as an adhesion layer.